1. Technical Field
The present invention relates to a semiconductor memory apparatus and a semiconductor memory apparatus including a latch circuit.
2. Related Art
A flash memory apparatus, which is a kind of a nonvolatile memory apparatus, programs or reads data in units of page. To this end, the flash memory apparatus includes a page buffer circuit to process large capacity data for a short time. The page buffer circuit includes a latch circuit in order to temporarily store data when programming (i.e., PGM as seen in FIG. 1) or reading the data.
FIG. 1 is a circuit diagram of a general semiconductor memory apparatus including a page buffer.
A semiconductor memory apparatus, such as a flash memory, is classified into a single level cell (SLC) apparatus, a multi-level cell (MLC) apparatus, and a triple level cell (TLC) apparatus according to bits of data storable per one memory cell. Therefore, the number of latch circuits required changes. FIG. 1 illustrates a page buffer in a general case, and mainly illustrates a latch circuit connected to an output data line in a SLC page buffer.
A semiconductor memory apparatus of FIG. 1 includes a memory cell 10, a page buffer 20, and a column selection unit 30.
The page buffer includes transistors N1 to N5 and P1 as well as ground voltage VSS. In a read operation, the page buffer 20 reads data from the memory cell 10 to output nodes QA and QAN. Then, if a column selection signal YI is applied to a corresponding column, the column selection unit 30 transmits the data to data lines DL and DLB.
The above operation will be described in detail as follows. Initially, a data latch section 21 is initialized by a reset signal RESET. If a precharge signal PRECHSO_N is activated, a sensing node SO is precharged at the level of an internal voltage VINT. Then, if a sensing signal PB_SENSE is activated, data transferred through a bit line BL is transferred to the sensing node SO. At this time, a voltage level of the sensing node SO is equal to or lower than a precharge voltage level according to the data value.
If a read command READ is applied, the data latch section 21 drives the output node QA to have the voltage level of the sensing node SO (the other output node QAN has an opposite voltage logic level) and to latch the value. If the column selection signal YI is applied, voltage levels of the output nodes QA and QAN are output to the data lines DL and DLB, respectively.
FIG. 2 is a configuration diagram illustrating a data output unit of a general semiconductor memory apparatus including the data latch section 21.
The data output unit of the general semiconductor memory apparatus includes an input/output sense amplifier 40 in order to amplify data of a small signal. When a plurality of data latch units 21_1, 21_2, to 21_n exist according to the number of page buffers and a corresponding column is selected by column selection units 30_1, 30_2, to 30_n, data stored in the data latch units 21_1 to 21_n is transmitted to and amplified by the input/output sense amplifier 40.
For example, when data of the first data latch unit 21_1 is read, the data is transmitted to the input/output sense amplifier 40 by the first column selection unit 30_1, and the input/output sense amplifier 40 senses and amplifies the received data.
When the first data latch unit 21_1 transmits a high voltage logic level to data lines DL and DLB, a precharge voltage level is transmitted as is. Meanwhile, when it is necessary to transmit a low voltage logic level, the precharge voltage level should be driven to a low voltage logic level for transmission. However, since the capacities of transistors N6 and N7 used in the first column selection unit 30_1 are large, inverters IV1 and IV2 included in the first data latch unit 21_1 are heavily loaded when driving low voltage logic level data. Therefore, although a good performing input/output sense amplifier 40 is used, much data detection time is required.
The problem with a data semiconductor memory apparatus due to a log loading time of the latch circuit is not limited only to a page buffer circuit, and may occur in all semiconductor memory apparatuses using a latch circuit.